Interrupt Operation; Interrupt Sequence - Hitachi SH7095 Hardware User Manual

Bit 15: NMIL
0
1
• Bits 14 to 9—Reserved bits: These bits always read 0. The write value should always be 0.
• Bit 8—NMI edge select (NMIE): Selects whether the falling or rising edge of the interrupt
request signal to the NMI is detected.
Bit 8: NMIE
0
1
• Bits 7 to 1—Reserved bits: These bits always read 0. The write value should always be 0.
• Bit 0—IRL interrupt vector mode select (VECMD): This bit selects whether to set the IRL
interrupt vector number to the auto-vector mode or the external vector mode. When the mode
is auto-vector, the internally determined vector number is set. The IRL15 and IRL14 interrupt
vector numbers are set to 71 and the IRL1 vector number is set to 64. When the mode is
external vector, a value between 0 and 127 can be input as the vector number from the
external vector number input pins (D7–D0).
Bit 0: VECMD
0
1
5.4

Interrupt Operation

5.4.1

Interrupt Sequence

The sequence of interrupt operations (figure 5.5) is explained below:
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,
following the priority levels set in interrupt priority level setting registers A and B (IPRA and
IPRB). Lower-priority interrupts are held pending. If two of these interrupts have the same
priority level or if multiple interrupts occur within a single module, the interrupt with the
highest default priority or the highest priority within its IPR setting unit (as indicated in table
5.4) is selected.
84 Hitachi
Description
NMI input level is low
NMI input level is high
Description
Interrupt request is detected on falling edge of NMI input (Initial value)
Interrupt request is detected on rising edge of NMI input
Description
Auto vector mode, set internally (Initial value)
External vector mode, external input