Hitachi SH7095 Hardware User Manual page 344

Bit 7: TDRE Description
0 TDR contains valid transmit data
TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE or the DMAC writes data in TDR.
1 TDR does not contain valid transmit data (initial value)
TDRE is set to 1 when the chip is reset or enters standby mode, the TE bit in the
serial control register (SCR) is cleared to 0, or TDR contents are loaded into
TSR, so new data can be written in TDR.
• Bit 6: Receive data register full (RDRF). Indicates that RDR contains received data.
Bit 6: RDRF Description
0 RDR does not contain valid received data (initial value)
RDRF is cleared to 0 when the chip is reset or enters standby mode, software
reads RDRF after it has been set to 1, then writes 0 in RDRF, or the DMAC
reads data from RDR.
1 RDR contains valid received data.
RDRF is set to 1 when serial data is received normally and transferred from RSR
to RDR.
Note: The RDR and RDRF are not affected by detection of receive errors or by clearing of the RE
bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set
to 1 when reception of the next data ends, an overrun error (ORER) occurs and the
received data is lost.
• Bit 5: Overrun error (ORER). Indicates that data reception ended abnormally due to an
overrun error.
Bit 5: ORER Description
0 Receiving is in progress or has ended normally (initial value).
ORER is cleared to 0 when the chip is reset or enters standby mode or software
reads ORER after it has been set to 1, then writes 0 in ORER.
1 A receive overrun error occurred.
ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1.
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which
retains its previous value.
2. RDR continues to hold the data received before the overrun error, so subsequent
receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the
clocked synchronous mode, serial transmitting is disabled.
• Bit 4: Framing error (FER). Indicates that data reception ended abnormally due to a framing
error in the asynchronous mode.
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