Hitachi SH7095 Hardware User Manual page 203

There are three modes for bus arbitration: master mode, partial-share master mode, and slave
mode. Master mode keeps the bus under normal conditions and permits other devices to use the
bus by releasing it when they request its use. The slave mode normally does not have the bus. It
requests the bus when an external bus access cycle comes up and then releases the bus when the
access is completed. The partial-share master mode only shares CS2 space with external devices .
For the CS2 space, it is in slave mode; for other spaces, it always keeps the bus without any bus
arbitration. The CS space onto which the chip in master mode the chip in partial-share master
mode CS2 space is allocated is determined by the externally connected circuits.
Master or slave mode can be specified using external mode pins. Partial-share master mode is
reached from master mode by setting software. See Section 3, Oscillator Circuits and Operating
Mode, for the external mode pin setting. When a device in master or slave mode does not have the
bus, its bus goes to high impedance, so master mode chips and slave mode chips can be connected
directly. In the partial-share master mode, the bus is always driven, so an external buffer is needed
to connect to a master bus. In master mode, a connection to an external device requesting the bus
can be substituted for the slave mode connection. In the following explanation, external devices
requesting the bus are also called slaves.
The SH7095 has two internal bus masters, the CPU and the DMAC. When an synchronous
DRAM, DRAM or pseudo SRAM is connected and refresh control being performed, the refresh
request becomes a third master. In addition to these, there are also bus requests from external
devices while in the master mode. The priority for bus requests when they occur simultaneously is,
highest to lowest, refresh requests, bus requests from external devices, DMAC and CPU.
When the bus is being passed between slave and master, all bus control signals are negated before
the bus is released to prevent the connected devices from operating in error. Once the bus is
received, the bus control signals change from negated to bus driven. The master and slave passing
the bus between them drive the same signal values, so output buffer conflict is avoided. Turning
the output buffer off for the bus control signals on the side that releases the bus and on at the side
getting the bus can eliminate the high impedance period of the signals. It is usually not necessary
to insert a pull-up resistance into these control signals to prevent malfunction caused by external
noise while they are at high impedance.
Bus permission is performed at the end of the bus cycle. When the bus is requested, the bus is
released immediately if there is no ongoing bus cycle. If there is a current bus cycle, the bus is not
released until the bus cycle ends. Even when there does not appear to be an ongoing bus cycle
when seen from outside the SH7095, it cannot be determined whether or not the bus will be
released immediately when a bus control signal such as a CSn signal is seen, since an internal bus
cycle, such as inserting a wait between access cycles, may have been started. The bus cannot be
released during burst transfers for cache fills or 16-byte DMAC block transfers. Likewise, the bus
cannot be released between the read and write cycles of a TAS instruction. Arbitration is also not
performed between multiple bus cycles produced by a data width smaller than the access size,
such as a longword access to an 8-bit data width memory. Bus arbitration is performed between
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