Hitachi SH7095 Hardware User Manual page 199

performed. Figure 7.45 shows the relationship between data width and access size. For cache fills
and DMAC 16-byte transfers, longword accesses are repeated 4 times.
When one or more wait states are set for a burst ROM access, the WAIT pin is sampled. When the
burst ROM is set and 0 indicated for waits, there are 2 access cycles from the second time on.
Figure 7.46 shows the timing.
Figure 7.44 Burst ROM Nibble Access (2 Wait States)
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