Hitachi SH7095 Hardware User Manual page 123

The instruction at address H'00037226 will be executed and then a user break interrupt will occur
before the instruction at address H'0003722E is executed.
(C) Register settings:
Conditions set (A ch/B ch independent mode):
A ch:
B ch:
A user break interrupt is not generated for channel A since the instruction fetch is not a write
cycle. A user break interrupt is not generated for channel B because the instruction fetch is for an
odd address.
(D) Register settings:
Conditions set (A ch to B ch sequential mode):
A ch:
B ch:
The break for channel A is a write cycle, so conditions are not satisfied; since the sequence
conditions are not met, no user break interrupt occurs.
Break on CPU Data Access Cycle:
Register settings:
112 Hitachi
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A
BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054
BDRB = H'00000000, BDMRB = H'00000000
BRCR = H'1000
Address = H'00027128, address mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), write , word
Address = H'00031415, address mask H'00000000
Data H'00000000, data mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), read
(operand size not included in conditions)
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A
BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056
BDRB = H'00000000, BDMRB = H'00000000
BRCR = H'1010
Address = H'00037226, address mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), write, word
Address = H'0003722E, address mask H'00000000
Data H'00000000
Data mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), read, word
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064
BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A
BDRB = H'0000A512, BDMRB = H'00000000
BRCR = H'1000