Hitachi SH7095 Hardware User Manual page 279

Transfer Width: 16-byte
Transfer bus mode: Cycle steal mode
Transfer address mode: Dual mode
DREQ detection method: Level detection
DACK output timing: DMAC write cycle
Bus cycle: Basic bus cycle
Note: Request detection
Figure 9.44 Timing of DREQ Pin Input Detection in Cycle Steal Mode
For 16-byte transfers, DACK signals are output at all consecutive writes (figure 9.44). The
acknowledge signals are A1, A2, A3, A4, B1, B2, B3, B4, ....
The second transfer request can be detected 2 cycles after output of acknowledge signal A1.
The third transfer request is detected at A3, that is, 2 cycles after output of the third
acknowledge signal of the first transfer. The fourth transfer request is detected 2 cycles after
output of B3. Requests thereafter are detected 2 cycles after the third acknowledge signal of
each transfer, as with the fourth transfer.
Note: When transferring alternately on ch0 and ch1 by round robin or the like, the next
request signal is detected only 2 cycles after the first acknowledge signal of each transfer
(figure 9.45).
268 Hitachi
with Level Detection (4)