Hitachi SH7095 Hardware User Manual page 4

4.1.1 Types of Exception Processing and Priority Order....................................... 53
4.1.2 Exception Processing Operations ............................................................. 54
4.1.3 Exception Processing Vector Table .......................................................... 55
4.2 Resets............................................................................................................ 57
4.2.1 Types of Resets .................................................................................... 57
4.2.2 Power-On Reset ................................................................................... 57
4.2.3 Manual Reset....................................................................................... 58
4.3 Address Errors ................................................................................................ 59
4.3.1 Sources of Address Errors ...................................................................... 59
4.3.2 Address Error Exception Processing......................................................... 60
4.4 Interrupts ....................................................................................................... 60
4.4.1 Interrupt Sources .................................................................................. 60
4.4.2 Interrupt Priority Level .......................................................................... 61
4.4.3 Interrupt Exception Processing ................................................................ 61
4.5 Exceptions Triggered by Instructions................................................................... 62
4.5.1 Instruction-Triggered Exception Types ..................................................... 62
4.5.2 Trap Instructions .................................................................................. 62
4.5.3 Illegal Slot Instructions .......................................................................... 63
4.5.4 General Illegal Instructions..................................................................... 63
4.6 When Exception Sources are Not Accepted .......................................................... 63
4.6.1 Immediately after a Delay Branch Instruction............................................. 64
4.6.2 Immediately after an Interrupt-Disabled Instruction..................................... 64
4.7 Stack Status after Exception Processing Ends........................................................ 64
4.8 Notes on Use .................................................................................................. 65
4.8.1 Value of Stack Pointer (SP) .................................................................... 65
4.8.2 Value of Vector Base Register (VBR)....................................................... 65
4.8.3 Address Errors Caused by Stacking of Address Error Exception Processing ..... 65
4.8.4 Accessing Registers during a Manual Reset ............................................... 65
Section 5 Interrupt Controller (INTC)
5.1 Overview ....................................................................................................... 67
5.1.1 Features .............................................................................................. 67
5.1.2 Block Diagram..................................................................................... 67
5.1.3 Pin Configuration ................................................................................. 69
5.1.4 Register Configuration........................................................................... 69
5.2 Interrupt Sources ............................................................................................. 70
5.2.1 NMI Interrupts ..................................................................................... 70
5.2.2 User Break Interrupt.............................................................................. 70
5.2.3 IRL Interrupts ...................................................................................... 71
5.2.4 On-chip Peripheral Module Interrupts....................................................... 74
5.2.5 Interrupt Exception Vectors and Priority Rankings ...................................... 74
5.3 Description of Registers.................................................................................... 76
5.3.1 Interrupt Priority Level Setting Register A (IPRA) ...................................... 76
............................................................... 67
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