Partial-Share Master Mode - Hitachi SH7095 Hardware User Manual

Figure 7.49 Master and Slave Connection
7.10.3 Partial -Share Master Mode
In the partial-share master mode, only CS2 space is shared with other devices. Other CS spaces
can always be accessed. To set for the partial-share master mode, set to master mode using the
external mode pins and then set the PSHR bit of the BCR to 1 in the power-on reset initialization
procedure. During a manual reset, the values of the bus state controller setting registers are held,
so they do not need to be set again.
The partial-share master mode is designed to be used with a chip in the master mode. Figure 7.50
shows an example of connections between the partial-share master mode and a chip in master
mode. On the master mode side, the CS3 space is connected to synchronous DRAM and the CS0
space to ROM. On the partial-share master mode side, the CS0 space is connected to ROM, the
master side synchronous DRAM is connected to the CS2 space, and the CS3 space is connected to
dedicated synchronous DRAM. The partial-share master is also connected through the CS2 space
to the master synchronous DRAM so it can be accessed. The master, however, cannot access
devices on the partial-share master side. There is a buffer for addresses and control signals and a
buffer for data located between the partial-share master and the master. They are controlled by a
buffer control circuit. The buffers latch signals synchronous to the clock rise and match timing, so
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