Hitachi SH7095 Hardware User Manual page 241

Bit 5: DL
0
1
• Bit 4—Transfer Bus Mode Bit (TB): Selects the bus mode for DMA transfers. The TB bit is
initialized to 0 by reset and in the standby mode. Values are held during a module standby.
Bit 4: TB
0
1
• Bit 3—Transfer Address Mode Bit (TA): Selects the DMA transfer address mode. The TA bit
is initialized to 0 by reset and in the standby mode. Values are held during a module standby.
Bit 3: TA
0
1
• Bit 2—Interrupt Enable Bit (IE): Determines whether or not to request a CPU interrupt at the
end of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) is requested from the
CPU when the TE bit is set. The IE bit is initialized to 0 by reset and in the standby mode.
Values are held during a module standby.
Bit 2: IE
0
1
• Bit 1—Transfer-End Flag Bit (TE): Indicates that the transfer has ended. When the value in
the DMA transfer count register (TCR) becomes 0, the DMA transfer ends normally and the
TE bit is set to 1. This flag is not set if the transfer ends because of an NMI interrupt or DMA
address error, or because the DME bit of the DMA operation register (DMAOR) or the DE bit
was cleared. To clear the TE bit, read 1 from it and then write 0. When the TE bit is set,
setting the DE bit to 1 will not enable a transfer. The TE bit is initialized to 0 by reset and in
the standby mode. Values are held during a module standby.
230 Hitachi
Description
When DS is 0, DREQ is detected by low level; when DS is 1, DREQ is
detected by fall (Initial value)
When DS is 0, DREQ is detected by high level; when DS is 1, DREQ is
detected by rise
Description
Cycle-steal mode (Initial value)
Burst mode
Description
Dual address mode (Initial value)
Single address mode
Description
Interrupt disabled (Initial value)
Interrupt enabled