Bus Control Register 2 (Bcr2) - Hitachi SH7095 Hardware User Manual

Bit 5 (A0LW1) Bit 4 (A0LW0)
0 0
1
1 0
1
• Bits 2–0—Enable for DRAM and Other Memory (DRAM2–DRAM0)
DRAM2 DRAM1
0 0
1
1 0
1
7.2.2

Bus Control Register 2 (BCR2)

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Initialize BCR2 after a power-on reset and do not write to it thereafter. When writing to it, write
the same bits as those they are initialized to. Do not access any space other than CS0 until the
register initialization ends.
• Bits 15–8—Reserved bits: These bits always read 0. The write value should always be 0.
126 Hitachi
Description
3 waits (Initial value)
4 waits
5 waits
6 waits
DRAM0 Description
0 Areas 2 and 3 are ordinary spaces (Initial value)
1 Area 2 is ordinary space; area 3 is synchronous DRAM space
0 Area 2 is ordinary space; area 3 is DRAM space
1 Area 2 is ordinary space; area 3 is pseudo SRAM space
0 Area 2 is synchronous DRAM space, area 3 is ordinary space
1 Areas 2 and 3 are synchronous DRAM spaces
0 Reserved (do not set)
1 Reserved (do not set)
15 14
— —
0 0
R R
7 6
A3SZ1 A3SZ0
1 1
R/W R/W
13 12
— —
0 0
R R
5 4
A2SZ1 A2SZ0 A1SZ1
1 1
R/W R/W
11 10
— —
0 0
R R
3 2
A1SZ0
1 1
R/W R/W
9 8
— —
0 0
R R
1 0
— —
0 0
— —