Write - Hitachi SH7095 Hardware User Manual

the Td1 and Td2 cycles for longword accesses and only in the Td1 cycle for word or byte
accesses.
The empty cycle tends to increase the memory access time, lower the program execution speed,
and lower the DMA transfer speed, so it is important to avoid accessing unnecessary cache-
through area and to use data structures that enable 16-byte unit transfers by placing data on 16-
byte boundaries when performing DMA transfers that specify synchronous DRAM as the source.
Figure 7.17 Single Read Timing (Auto Precharge)
7.5.5

Write

Unlike synchronous DRAM reads, synchronous DRAM writes are single writes. Figure 7.18
shows the basic timing chart for write accesses. After the ACTV command Tr, a WRITA
command is issued in Tc to perform an auto precharge. In the write cycle, the write data is output
simultaneously with the write command. When writing with an auto precharge, the bank is
precharged after the completion of the write command within the synchronous DRAM, so no
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