Hitachi SH7095 Hardware User Manual page 99

Table 5.8 Interrupt Response Time
Item
Compare identified inter-
rupt priority with SR mask
level
Wait for completion of
sequence currently being
executed by CPU
Time from interrupt
exception processing (SR
and PC saves and vector
address fetches) until fetch
of first instruction of
exception service routine
starts
Interrupt
response
Minimum:10
Maximum:11 + 2 (m1 + m2 +
Note: m1–m4 are the number of states needed for the following memory accesses
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
88 Hitachi
Number of States
NMI Peripheral
module
2
X (≥ 0)
5 + m1 + m2 + m3
Total:7 + m1 + m2 + m3
m3) + m4
IRL
5
10 + m1 + m2 + m3 —
13
14 + 2 (m1 + m2 +
m3) + m4
Notes
—
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If
an interrupt-masking
instruction follows, however,
the time may be even
longer.
—
—
—