Master Mode - Hitachi SH7095 Hardware User Manual

external vector fetch, PC save and SR save cycles during interrupt processing, which are all
independent accesses.
Because the CPU on the SH7095 is connected to cache memory by a dedicated internal bus, cache
memory can be read even when the bus is being used by another bus master on the chip or
externally. Writing from the CPU always produces a write cycle externally since the write-through
system is adopted by the SH7095 for the cache. When an external bus address monitor is not
specified by the user break controller, the internal bus that connects the CPU, DMAC and on-chip
peripheral modules can operate in parallel to the external bus. This means that both read and write
accesses from CPU to on-chip peripheral modules and from DMAC to on-chip peripheral module
are possible. If an external bus address monitor is specified, the internal bus will be used for
address monitoring when the bus is passed to the external bus master, so accesses to on-chip
peripheral modules by the CPU and DMAC must wait for the bus to return.
7.10.1

Master Mode

Master mode processors keep the bus unless they receive a bus request. When a bus release
request (BRLS) assertion (low level) is received from an external device, buses are released and a
bus grant (BGR) is asserted (low level) as soon as the bus cycle being executed is completed.
When it receives a negated (high level) BRLS signal, indicating that the slave has released the bus,
it negates the BGR (to high level) and begins using the bus. When the bus is released, all output
and I/O signals related to the bus interface are changed to high impedance, except for the CKE of
the synchronous DRAM interface, the BGR of bus arbitration and DMA transfer control signals
DACK0 and DACK1.
When the DRAM or pseudo SRAM has finished precharging, the bus is released. The synchronous
DRAM also issues a precharge command to the active bank or banks. After this is completed, the
bus is released.
The specific bus release sequence is as follows. First, the bus use enable signal is asserted
synchronously with the fall of the clock. Half a cycle later, the address bus and data bus become
high impedance synchronous with the rise of the clock. Thereafter the bus control signals (BS,
CSn, RAS, CAS, WEn, RD, RD/WR, IVECF) become high impedance with the fall of the clock.
All of these signals are negated at least 1.5 cycles before they become high impedance. Sampling
for bus request signals occurs at the clock fall.
The sequence when the bus is taken back from the slave is as follows. When the negation of a
BRLS is detected at a clock fall, the BGR is immediately negated and the master simultaneously
starts to drive the bus control signals. The address bus and data bus are driven starting at the next
clock rise. The bus control signals are asserted and the bus cycle actually starts from the same
clock rise that the address and data signals are driven, in the fastest case. Figure 7.48 shows the
timing of bus arbitration in master mode.
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