Burst Access - Hitachi SH7095 Hardware User Manual

Figure 7.40 External Wait State Timing
7.7.4

Burst Access

In addition to normal access, in which the CE is alternatively asserted and negated at every access,
when consecutive accesses are to the same row address the pseudo SRAM can access data at high
speed by changing only the column address and leaving CE asserted. This function is called the
static column mode. Select between ordinary access and burst mode using static column mode by
setting the burst enable bit (BE) in the MCR. Figure 7.41 shows the timing of burst operation
using static column mode. When performing burst access, cycles can be inserted using the wait
state control function.
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