Address Multiplex - Hitachi SH7095 Hardware User Manual

Figure 7.30 Example of a DRAM Connection (16-Bit Data Width)
7.6.2

Address Multiplex

When CS3 space is set to DRAM, addresses are always multiplexed. This allows DRAMs that
require multiplexing of row and column addresses to be connected directly to SH7095
microprocessors without additional multiplexing circuits. There are four ways of multiplexing,
which can be selected using the MCR's AMX1–AMX0 bits. Table 7.5 illustrates the relationship
between AMX1/AMX0 bits and address multiplexing. Address multiplexing is performed on
address output pins A13–A1. The original addresses are output to the pins A26–A14. During
DRAM accesses, AMX2 is reserved, so set it to 0.
Table 7.5 Relationship between AMX1–AMX0 and Address Multiplexing
AMX1 AMX0
0 0
1
1 0
1
170 Hitachi
No. of Column
Address Bits
8 bits
9 bits
10 bits
11 bits
Row
Address Output
A21–A9
A22–A10
A23–A11
A24–A12
Column
Address Output
A13–A1
A13–A1
A13–A1
A13–A1