Hitachi SH7095 Hardware User Manual page 140

When area 3 is DRAM, the number of CAS assert cycles is specified by wait control W31 and
W30:
Bit 7 (W31)
0
1
When the setting is for 2 or more cycles, external wait input is enabled.
When area 2 or 3 is synchronous DRAM, CAS latency is specified by wait control W31 and
W30, and W21 and W20, respectively:
W31, W21
0
1
With synchronous DRAM, external wait input is ignored regardless of setting.
When area 3 is pseudo SRAM, the number of cycles from BS signal assertion to the end of
cycle is specified by wait control W31 and W30:
Bit 7 (W31)
0
1
When the setting is for 3 or more cycles, external wait input is enabled.
Bit 6 (W30)
0
1
0
1
W30, W20
0
1
0
1
Bit 6 (W30)
0
1
0
1
Description
1 cycle
2 cycles
3 cycles
Reserved (do not set)
Description
1 cycle
2 cycles
3 cycles
4 cycles
Description
2 cycles
3 cycles
4 cycles
Reserved (do not set)
Hitachi 129