Hitachi SH7095 Hardware User Manual page 505

WDT
Watchdog timer control/status
register (WTCSR)
Item 7
Bit name
OVF
Initial Value 0
R/W R/W
Bit Bit Name
7 Overflow flag (OVF)
6 Timer mode select
(WT/IT)
5 Timer enable (TME)
2 to 0 Clock select 2 to 0
(CKS2 to CKS0)
494 Hitachi
H'FFFFFE80
6 5
WT/IT TME
0 0
R/W R/W
Value
0 No overflow of WTCNT in interval timer mode (initial
value) Cleared by reading OVF, then writing 0 in OVF
1 WTCNT overflow in the interval timer mode
0 Interval timer mode: Interval timer interrupt (ITI) request
to the CPU when WTCNT overflows (initial value)
1 Watchdog timer mode: WDTOVF signal is output
externally when WTCNT overflows.
0 Timer disabled: WTCNT is initialized to H'00 and count-
up stops (initial value)
1 Timer enabled: WTCNT starts counting. A WDTOVF
signal or interrupt is generated when WTCNT overflows.
CKS2 CKS1 CKS0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
8 (read)
16(write)
Bit
4 3
– – CKS2
1 1
– – R/W
Description
Clock Source
φ/2(initial value)
0
φ/64
1
φ/128
0
φ/256
1
φ/512
0
φ/1024
1
φ/4096
0
φ/8192
1
2 1
CKS1 CKS0
0 0
R/W
Overflow Interval
(φ = 28.7 MHz)
17.8µs
570.8µs
1.1ms
2.2ms
4.5ms
9.1ms
35.5ms
73.0ms
0
0
R/W