Hitachi SH7095 Hardware User Manual page 383

Simultaneous Multiple Receive Errors: Table 13.14 indicates the state of the SSR status flags
when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR
contents cannot be transferred to the RDR, so receive data is lost.
Table 13.14 SSR Status Flags and Transfer of Receive Data
Receive Error Status
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity
error
O: Receive data is transferred from RSR–RDR.
X: Receive data is not transferred from RSR–RDR.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of
all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI
receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.
Sending a Break Signal: When TE is cleared to 0, a 1 is output from the TxD pin.
Receive Error Flags and Transmitter Operation (clocked synchronous mode only): When a
receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if
TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that
clearing RE to 0 does not clear the receive error flags.
Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode: In the
asynchronous mode, the SCI operates on a base clock of 16 times the bit rate frequency. In
receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on
the base clock. Receive data is latched on the rising edge of the eighth base clock pulse. See figure
13.21.
372 Hitachi
SSR Status Flags
RDRF ORER
1 1
0 0
0 0
1 1
1 1
0 0
1 1
Receive Data
Transfer
FER PER RSR
0 0 X
1 0 O
0 1 O
1 0 X
0 1 X
1 1 O
1 1 X
RDR