Notes: 1.
Dotted lines indicate a synchronous DRAM in another CS space is connected.
2.
The DACKn waveform shown is for the case where active high has been
specified.
Figure 15.22 Synchronous DRAM Read Bus Cycle
(RCD = 2 Cycle, CAS Latency = 2 Cycle, Bursts = 4)
414 Hitachi