Sh7000-Series Compatibility Mode - Hitachi SH7095 Hardware User Manual

3. When set for sequential conditions (the SEQ bit of BRCR is 1) and the instruction fetch cycle
of the A channel CPU is set as a condition, set channel A for before instruction execution
(PCBA bit of BRCR is 0).
4. When register settings are changed, the write values usually become valid after three cycles.
For on-chip memory, instruction fetches get two instructions simultaneously. If a break
condition is set on the fetch of the second of these two instructions but the contents of the
UBC registers are changed so as to alter the break condition immediately after the first of the
two instructions is fetched, a user break interrupt will still occur before the second instruction.
To ensure the timing of the change in the setting, read the register written last as a dummy.
The changed settings will be valid thereafter.
5. When a user break interrupt is generated upon a match of the instruction fetch condition and
the conditions match again in the UBC while the exception processing service routine is
executing, the break will cause exception processing when the I3–I0 bits of the SR are set to
14 or lower. When masking addresses, when setting instruction fetch and after-execution as
break conditions, and when executing in steps, the UBC's exception processing service
routine should not cause a match of addresses with the UBC.
6. When the emulator is used, the UBC is used on the emulator system side to implement the
emulator's break function. This means none of the UBC functions can be used when the
emulator is being used.
6.3.8

SH7000-Series Compatibility Mode

1. In SH7000-series compatible mode:
In SH7000-series compatible mode, functions are as follows:
• The registers shown in the lower table in section 1.3, Register Configuration, are valid; all
others are not.
• External bus breaks are not possible in SH7000 mode. The instruction fetch cycle occurs
prior to instruction execution. The flags are not set when break conditions match.
2. Differences between SH7000 compatible mode and SH7095 mode:
When set for CPU instruction fetch cycle in the SH7000-series compatible mode, the break
occurs before the instruction that matches the conditions. The break conditions differ as
shown below from setting for before-execution in SH7095 mode. For data access cycles, the
address is always compared to 32 bits in the SH7000-series compatible mode, but in SH7095
mode is compared as shown in table 6.3. This produces the differences in break conditions
shown in table 6.4.
114 Hitachi