DIVU
Divisor register (DVSR)
Item
31
Bit name
Initial Value
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Item
15
Bit name
Initial Value
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
(Writes the divisor)
Dividend register L for 32-bit
division (DVDNT)
Item
31
Bit name
Initial Value
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Item
15
Bit name
Initial Value
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0 (Sets the dividend)
496 Hitachi
H'FFFFFE00
30
29
28
27
–
–
–
–
14
13
12
11
–
–
–
–
Bit nam
H'FFFFFE04
30
29
28
27
–
–
–
–
14
13
12
11
–
–
–
–
Bit nam
Sets the 32-bit dividend used for 32 bit/32 bit division
operations
Bit
26
25
24
23
–
–
–
–
10
9
8
7
–
–
–
–
Writes the divisor for the operation
Bit
26
25
24
23
–
–
–
–
10
9
8
7
–
–
–
–
32
22
21
20
19
–
–
–
–
6
5
4
3
–
–
–
–
Description
32
22
21
20
19
–
–
–
–
6
5
4
3
–
–
–
–
Description
18
17
16
–
–
–
2
1
0
–
–
–
18
17
16
–
–
–
2
1
0
–
–
–