Register Descriptions; System Control Register 1 (Syscr1) - Hitachi H8/3664 Hardware Manual

6.2

Register Descriptions

6.2.1

System Control Register 1 (SYSCR1)

Bit 7
SSBY
Initial value 0
Read/Write R/W
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'00.
Bit 7—Software Standby (SSBY): This bit designates the transition to the sleep mode, subsleep
mode, or standby mode.
Bit 7: SSBY
0
1
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the
CPU and peripheral modules wait for stable clock operation after exiting from the standby mode,
subactive mode, or subsleep mode to the active mode or sleep mode due to an interrupt. The
designation should be made according to the clock frequency so that the waiting time is at least 10
ms.
Bit 6: STS2 Bit 5: STS1
0 0
1
1 0
1
82
6
STS2 STS1
0
R/W R/W
Description
When a SLEEP instruction is executed in the active mode, a transition is made
to the sleep mode or subsleep mode.
When a SLEEP instruction is executed in the active mode, a transition is made
to the standby mode.
Bit 4: STS0
0
1
0
1
0
1
0
1
5 4
STS0 NESEL
0 0
R/W R/W
Description
Wait time = 8,192 states
Wait time = 16,384 states
Wait time = 32,768 states
Wait time = 65,536 states
Wait time = 131,072 states
Wait time = 1,024 states
Wait time = 128 states
Wait time = 16 states
3 2
—
0 0
—
1 0
— —
0 0
— —
(Initial value)
(Initial value)