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3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3022 Series.
Bit
SSBY
Initial value
Read/Write
R/W
Software standby
Enables transition to software standby mode
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 17, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit7
SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
58
7
6
STS2
STS1
0
0
R/W
R/W
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
5
4
STS0
UE
0
0
R/W
R/W
User bit enable
Selects whether to use UI bit in CCR
as a user bit or an interrupt mask bit
3
2
NMIEG
1
0
R/W
Reserved bit
NMI edge select
Selects the valid edge
of the NMI input
1
0
—
RAME
1
1
—
R/W
RAM enable
Enables or
disables
on-chip RAM
(Initial value)
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