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10.2
System Control Register
The system control register (SYSCR) selects the clock for the CPU.
Table 10.1 System Control Register
Register
System control register
Bit:
Initial value:
Read/Write:
SYSCR is initialized to H'00 at reset, but not reset in sleep mode. The CPUCS0 bit in SYSCR can
be written to only once before TCWA in WDT is written to. When the TCWA function is not
used, it can be written to only once before TCSR in WDT is written to. Once written to, it cannot
be written to again until the chip is reset by a low-level input to the RES pin.
Bits 7 to 1 —Reserved: Always read as 0 and cannot be written to.
Although not used at present, the reserved bits may be used in the future. When writing to
SYSCR, write 0 to these bits.
Bit 0—CPU Clock Select 0 (CPUCS0): Selects the CPU operating clock. When CPUCS0 = 0,
the CPU operates at half of the external clock frequency. When CPUCS0 = 1, the CPU operates at
the external clock frequency. When a value is set to the CPUCS0 bit, the setting becomes valid in
the CPU cycle following the CPUCS0 setting cycle.
Bit 0: CPUCS0
Description
0
The CPU operates at half of the external clock frequency
1
The CPU operates at the external clock frequency
104
Abbr.
SYSCR
7
6
5
—
—
—
0
0
0
R
R
R
R/W
Initial Value
R/W
H'00
4
3
2
—
—
—
0
0
0
R
R
R
Address
H'FFF4
1
0
—
CPUCS0
0
0
R
R/W
(Initial value)
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