System Control Register (Syscr) - Hitachi H8S/2678 Series Reference Manual

2.2.2

System Control Register (SYSCR)

Bit 7
—
Initial value 1
Read/Write R/W
Note: * Determined by pins MD2 to MD0.
Bits 7 and 6—Reserved: These are readable/writable bits, but the write value should always be 1.
Bit 5—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the
MAC instruction.
Bit 5
MACS Description
0 Non-saturating calculation for MAC instruction
1 Saturating calculation for MAC instruction
Bit 4—Reserved: This is a readable/writable bit, but the write value should always be 0.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details see section 18,
ROM, in the H8S/2678 Series Hardware Manual.
In the mask ROM and ROMless versions, 0 should be written to this bit.
Bit 3
FLSHE Description
0 Flash memory control registers are not selected for area H'FFFFC8 to H'FFFFCB
1 Flash memory control registers are selected for area H'FFFFC8 to H'FFFFCB
Bit 2—Reserved: This bit is always read as 0 and cannot be modified. The write value should
always be 0.
Bit 1—External Bus Mode Enable (EXPE): Sets external bus mode.
In modes 1, 2, 4, 5, 6, 10, 12, 13, and 14, this bit is fixed at 1 and cannot be modified. In modes 7,
11, and 15, this bit has an initial value of 0, and can be read and written.
34
6 5
— MACS
1 0
R/W R/W
4 3
— FLSHE
0 0
R/W R/W
2 1
— EXPE RAME
0 —*
— R/W
(Initial value)
(Initial value)
0
1
R/W