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9.2 Register Descriptions
9.2.1 A/D Data Registers (ADDR)—H'FFE0 to H'FFE6
Bit
7
ADDRn
Initial value
0
Read/Write
R
The four A/D data registers (ADDRA to ADDRD) are 8-bit read-only registers that store the results
of A/D conversion. Each data register is assigned to two analog input channels as indicated in
table 9-3.
The A/D data registers are always readable by the CPU.
The A/D data registers are initialized to H'00 at a reset and in the standby modes.
Table 9-3. Assignment of Data Registers to Analog Input Channels
Analog input channel
Group 0
Group 1
AN
AN
0
4
AN
AN
1
5
AN
AN
2
6
AN
AN
3
7
9.2.2 A/D Control/Status Register (ADCSR)—H'FFE8
Bit
7
ADF
Initial value
0
Read/Write
R/(W)*
Note: * Software can write a "0" in bit 7 to clear the flag, but cannot write a "1" in this bit.
The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the
operation of the A/D converter module.
6
5
0
0
R
R
A/D data register
ADDRA
ADDRB
ADDRC
ADDRD
6
5
ADIE
ADST
0
0
R/W
R/W
4
3
2
0
0
0
R
R
R
4
3
2
SCAN
CKS
CH2
0
0
0
R/W
R/W
R/W
212
1
0
0
0
R
R
(n = A to D)
1
0
CH1
CH0
0
0
R/W
R/W
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