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17.3.2
A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit
Bit Name
7
ADF
6
ADIE
5
ADST
Initial Value
R/W
0
R/(W)
0
R/W
0
R/W
Description
A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
•
When A/D conversion ends
•
When A/D conversion ends on all specified
channels
[Clearing conditions]
•
When 0 is written after reading ADF = 1
•
When the DTC is activated by an ADI interrupt
and ADDR is read
A/D Interrupt Enable
A/D conversion end interrupt (ADI) is enabled when
this bit is set to 1.
A/D Start
Clearing this bit to 0 stops A/D conversion, and the
A/D converter enters the wait state.
Setting this bit to 1 starts A/D conversion. In single
mode, this bits is automatically cleared to 0 when
conversion on the specified channel is complete. In
scan mode, conversion continues sequentially on
the specified channels until this bit is cleared to 0
by software, a reset, or a transition to software
standby mode, hardware standby mode or module
stop mode.
Rev. 1.0, 09/02, page 431 of 568
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