A/D Control/Status Register (Adcsr) - Hitachi H8/3664 Hardware Manual

The CPU can always read the A/D data registers. The upper byte can be read directly, but the
lower byte is read through a temporary register (TEMP). For details see section 16.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 16.3 Analog Input Channels and A/D Data Registers (ADDRA to ADDRD)
Analog Input Channel
Group 0 Group 1
AN0 AN4
AN1 AN5
AN2 AN6
AN3 AN7
16.2.2

A/D Control/Status Register (ADCSR)

Bit
ADF
Initial value
Read/Write R/(W)
A/D end flag
Indicates end of A/D conversion
Note: * Only 0 can be written, to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
7 6
ADIE ADST
0 0
* R/W R/W
A/D start
Starts or stops A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
5 4
SCAN CKS
0 0
R/W R/W
Clock select
Selects the A/D conversion time
Scan mode
Selects single mode or scan mode
3 2
CH2 CH1
0 0
R/W R/W
Channel select 2 to 0
These bits select analog
input channels
1 0
CH0
0 0
R/W
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