External Trigger Input Timing - Hitachi H8/3006 Hardware Manual

Table 15.4 A/D Conversion Time (Single Mode)
Synchronization delay
Input sampling time
A/D conversion time
Note: Values in the table are numbers of states.
15.4.4

External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR and the 8-bit
timer's ADTE bit is cleared to 0, external trigger input is enabled at the ADTRG pin. A falling
edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other
operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by
software. Figure 15.6 shows the timing.
φ
ADTRG
Internal trigger
signal
ADST
530
Symbol Min
t 6
D
t —
SPL
t 131
CONV
Figure 15.6 External Trigger Input Timing
CKS = 0
Typ Max Min
— 9 4
31 — —
— 134 69
A/D conversion
CKS = 1
Typ Max
— 5
15 —
— 70