External Trigger Input Timing - Hitachi H8/329 Series Hardware Manual

Table 9-4 (a). A/D Conversion Time (Single Mode)
Item
Synchronization delay
Input sampling time
Total A/D conversion time t
Table 9-4 (b). A/D Conversion Time (Scan Mode)
Item
Synchronization delay
Input sampling time
Total A/D conversion time t
Note: Values in the tables above are numbers of states.

9.3.4 External Trigger Input Timing

A/D conversion can be started by external trigger input at the ADTRG pin. This input is enabled or
disabled by the TRGE bit in the A/D control register (ADCR). If the TRGE bit is set to "1," when
a falling edge of ADTRG is detected the ADST bit is set to "1" and A/D conversion begins.
Subsequent operation in both single and scan modes is the same as when the ADST bit is set to "1"
by software.
Figure 9-5 shows the trigger timing.
CKS = "0"
Symbol Min Typ
t 18 —
D
t — 63
SPL
227 —
CONV
CKS = "0"
Symbol Min Typ
t 18 —
D
t — 63
SPL
259 —
CONV
223
CKS = "1"
Max Min Typ
33 10 —
— — 31
242 115 —
CKS = "1"
Max Min Typ
33 10 —
— — 31
274 131 —
Max
17
—
122
Max
17
—
138