External Trigger Input Timing - Hitachi H8/3664 Hardware Manual

Table 16.4 A/D Conversion Time (Single Mode)
Synchronization delay
Input sampling time
A/D conversion time
Note: Values in the table are numbers of states.
16.4.4

External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger input is enabled at the ADTRG pin. A rising or falling edge on the ADTRG input pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 16.6 shows the
timing.
φ
ADTRG
Internal trigger
signal
ADST
Symbol Min
t 6
D
t —
SPL
t 131
CONV
Figure 16.6 External Trigger Input Timing
CKS = 0
Typ Max Min
— 9
31 —
— 134
A/D conversion
CKS = 1
Typ Max
4 — 5
— 15 —
69 — 70
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