Timing Of Setting Of Watchdog Timer Reset Bit (Wrst) - Hitachi H8/3006 Hardware Manual

12.3.4

Timing of Setting of Watchdog Timer Reset Bit (WRST)

The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3006 and H8/3007 chip. This internal reset signal clears OVF to 0, but
the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
φ
TCNT
Overflow signal
OVF
WDT internal
reset
WRST
Figure 12.7 Timing of Setting of WRST Bit and Internal Reset
422
H'FF H'00