External Trigger Input Timing - Hitachi SH7709S Hardware Manual

Table 20.4 A/D Conversion Time (Single Mode)
A/D conversion start
delay
Input sampling time
A/D conversion time
Note: Values in the table are numbers of states (t
20.4.5

External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGE1 and TRGE0 bits are set to 1 in
ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the
ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations,
regardless of the conversion mode, are the same as if the ADST bit had been set to 1 by software.
Figure 20.7 shows the timing.
Pø
ADTRG
External
trigger signal
ADST
634
Symbol Min
t 17
D
t —
SPL
t 514
CONV
Figure 20.7 External Trigger Input Timing
CKS = 0
Typ Max Min
— 28 10
129 — —
— 525 259
).
cyc
A/D conversion
CKS = 1
Typ Max
— 17
65 —
— 266