External Reset Of Tcnt - Hitachi H8/329 Series Hardware Manual

(3) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR,
the timer counter can be cleared when compare-match A or B occurs. Figure 7-7 shows the timing
of this operation.
Ø
ø
Internal
compare-match
signal
TCNT

7.3.3 External Reset of TCNT

When the CCLR1 and CCLR0 bits in the TCR are both set to "1," the timer counter is cleared on
the rising edge of an external reset input. Figure 7-8 shows the timing of this operation. The timer
reset pulse width must be at least 1.5 system clock periods.
Ø
ø
External reset
input (TMRI)
Internal clear
pulse
TCNT
N
Figure 7-7. Timing of Compare-Match Clear
N – 1
Figure 7-8. Timing of External Reset
155
H'00
N H'00