I2C Master Mode - ST STM32F101xx Reference Manual

RM0034
2
24.3.3 I C master mode
In Master mode, the I
serial data transfer always begins with a Start condition and ends with a Stop condition.
Master mode is selected as soon as the Start condition is generated on the bus with a
START bit.
The following is the required sequence in master mode.
● Program the peripheral input clock in I2C_CR2 Register in order to generate correct
timings
●
Configure the clock control registers
●
Configure the rise time register
●
Program the I2C_CR1 register to enable the peripheral
●
Set the START bit in the I2C_CR1 register to generate a Start condition
The peripheral input clock frequency must be at least:
●
2 MHz in Standard mode
●
4 MHz in Fast mode
Start condition
Setting the START bit causes the interface to generate a Start condition and to switch to
Master mode (M/SL bit set) when the BUSY bit is cleared.
Note: In master mode, setting the START bit causes the interface to generate a ReStart condition
at the end of the current byte transfer.
Once the Start condition is sent:
●
The SB bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address (see
2
C interface initiates a data transfer and generates the clock signal. A
Figure 238 & Figure 239
Inter-integrated circuit (I
Transfer sequencing EV5).
2
C) interface
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