Usart Mode Configuration; Usart Registers; Status Register (Usart_Sr); Table 97. Usart Mode Configuration - ST STM32F207 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
24.5

USART mode configuration

Asynchronous mode
Hardware flow control
Multibuffer communication (DMA)
Multiprocessor communication
Synchronous
Smartcard
Half-duplex (single-wire mode)
IrDA
LIN
1. X = supported; NA = not applicable.
24.6

USART registers

Refer to
used in register descriptions.
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
24.6.1

Status register (USART_SR)

Address offset: 0x00
Reset value: 0x00C0 0000
31 30 29
15 14 13
Reserved
670/1381

Table 97. USART mode configuration

USART modes
Section 1.1: List of abbreviations for registers
28 27 26 25
12 11 10 9
CTS
rc_w0
USART USART
1 2
X X
X X
X X
X X
X X
X X
X X
X X
X X
24 23 22
Reserved
8 7 6
LBD TXE TC RXNE
rc_w0 r rc_w0 rc_w0
RM0033 Rev 9
(1)
USART
UART4 UART5
3
X X X
X NA NA
X X X
X X X
X NA NA
X NA NA
X X X
X X X
X X X
for registers for a list of abbreviations
21 20 19 18
5 4 3 2
IDLE ORE NF
r r r
RM0033
USART
6
X
X
X
X
X
X
X
X
X
17 16
1 0
FE PE
r r