Sdio Data Fifo Register (Sdio_Fifo); Sdio Register Map; Table 134. Sdio Register Map - ST STM32F205 series Reference Manual

RM0033
26.9.15

SDIO data FIFO register (SDIO_FIFO)

Address offset: 0x80
Reset value: 0x0000 0000
The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs
contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store
multiple operands to read from/write to the FIFO.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
bits 31:0 FIFOData: Receive and transmit FIFO data
26.9.16

SDIO register map

The following table summarizes the SDIO registers.
Offset Register
0x00 SDIO_POWER
0x04 SDIO_CLKCR
0x08 SDIO_ARG
0x0C SDIO_CMD
0x10 SDIO_RESPCMD
0x14 SDIO_RESP1
0x18 SDIO_RESP2
0x1C SDIO_RESP3
0x20 SDIO_RESP4
0x24 SDIO_DTIMER
0x28 SDIO_DLEN
0x2C SDIO_DCTRL
0x30 SDIO_DCOUNT
The FIFO data occupies 32 entries of 32-bit words, from address:
SDIO base + 0x080 to SDIO base + 0xFC.

Table 134. SDIO register map

Reserved
Reserved
Secure digital input/output interface (SDIO)
FIF0Data
CMDARG
Reserved
CARDSTATUS1
CARDSTATUS2
CARDSTATUS3
CARDSTATUS4
DATATIME
DATALENGTH
RM0033 Rev 8
9 8 7 6 5
DATACOUNT
4 3 2 1 0
RESPCMD
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792