Interrupt Sources And Priorities - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
Table 5-2. Interrupt and PTS Control and Status Registers (Continued)
Mnemonic Address
EPA_PEND 1FA2H, 1FA3H
EPA_PEND1 1FA6H
EPAIPV 1FA8H
INT_MASK 0008H
INT_MASK1 0013H
INT_PEND 0009H
INT_PEND1 0012H
PSW No direct access
PTSSEL 0004H, 0005H
PTSSRV 0006H, 0007H
5.3

INTERRUPT SOURCES AND PRIORITIES

Table 5-3 lists the interrupts sources, their default priorities (30 is highest and 0 is lowest), and
their vector addresses. The unimplemented opcode and software trap interrupts are not priori-
tized; they go directly to the interrupt controller for servicing. The priority encoder determines
the priority of all other pending interrupt requests. NMI has the highest priority of all prioritized
interrupts, PTS interrupts have the next highest priority, and standard interrupts have the lowest.
The priority encoder selects the highest priority pending request and the interrupt controller se-
5-4
EPA Interrupt Pending Registers
The bits in these registers are set by hardware to indicate that a
multiplexed EPA interrupt is pending.
EPA Interrupt Priority Vector
This register contains a number from 00H to 14H corresponding to
the highest-priority pending EPA x interrupt source. This value
allows software to branch via the TIJMP instruction to the correct
interrupt service routine when the EPAx interrupt is activated.
Reading this register clears the pending bit of the associated
interrupt source. The EPA x pending bit (INT_PEND.7) is cleared
when all the pending bits for its sources (in EPA_PEND and
EPA_PEND1) have been cleared.
Interrupt Mask Registers
These registers enable/disable each maskable interrupt (that is,
each interrupt except unimplemented opcode, software trap, and
NMI).
Interrupt Pending Registers
The bits in this register are set by hardware to indicate that an
interrupt is pending.
Processor Status Word
This register contains one bit that globally enables or disables
servicing of all maskable interrupts and another that enables or
disables the PTS. These bits are set or cleared by executing the
enable interrupts (EI), disable interrupts (DI), enable PTS (EPTS),
and disable PTS (DPTS) instructions.
PTS Select Register
This register selects either a PTS routine or a standard interrupt
service routine for each of the maskable interrupt requests.
PTS Service Register
The bits in this register are set by hardware to request an end-of-
PTS interrupt.
Description