Interrupt Sources And Priorities - Intel 8XC196MC User Manual

8XC196MC, MD, MH USER'S MANUAL
Table 5-2. Interrupt and PTS Control and Status Registers (Continued)
Mnemonic Address
PI_PEND 1FBEH
PSW No direct access
PTSSEL 0004H, 0005H
PTSSRV 0006H, 0007H
5.3

INTERRUPT SOURCES AND PRIORITIES

Table 5-3 lists the interrupts sources, their default priorities (30 is highest and 0 is lowest), and
their vector addresses. The unimplemented opcode and software trap interrupts are not priori-
tized; they go directly to the interrupt controller for servicing. The priority encoder determines
the priority of all other pending interrupt requests. NMI has the highest priority of all prioritized
interrupts, PTS interrupts have the next highest priority, and standard interrupts have the lowest.
The priority encoder selects the highest priority pending request and the interrupt controller se-
lects the corresponding vector location in special-purpose memory. This vector contains the start-
ing (base) address of the corresponding PTS control block (PTSCB) or interrupt service routine.
PTSCBs must be located on a quad-word boundary in the internal register file.
5-4
Peripheral Interrupt Pending
Any bit set indicates a pending interrupt request.
Processor Status Word
This register contains one bit that globally enables or disables
servicing of all maskable interrupts and another that enables or
disables the PTS. These bits are set or cleared by executing the
enable interrupts (EI), disable interrupts (DI), enable PTS (EPTS),
and disable PTS (DPTS) instructions.
PTS Select Register
This register selects either a PTS routine or a standard interrupt
service routine for each of the maskable interrupt requests.
PTS Service Register
The bits in this register are set by hardware to request an end-of-
PTS interrupt.
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