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Intel Altera Agilex 7 FPGA I Series User Manual
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Intel Altera Agilex 7 FPGA I Series User Manual

Intel Altera Agilex 7 FPGA I Series User Manual

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Agilex
7 FPGA I-Series
Development Kit User Guide
683288
Online Version
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2024.04.05
UG-20338

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Summary of Contents for Intel Altera Agilex 7 FPGA I Series

  • Page 1 ™ Agilex 7 FPGA I-Series Development Kit User Guide 683288 Online Version Send Feedback 2024.04.05 UG-20338...

  • Page 2: Table Of Contents

    2.1. About Quartus Prime Software................9 2.1.1. Activating Your License................9 2.2. Development Board Package................... 9 2.3. Installing the Intel FPGA Download Cable II Driver........... 10 3. Development Board Setup.....................11 3.1. Applying Power to the Development Board.............. 11 3.2. Default Switch Settings..................12 3.2.1.
  • Page 3 Contents A.8. FPGA Configuration....................52 A.9. Supported Configuration Modes................53 A.10. Memory Interfaces..................... 55 A.11. I2C........................55 A.12. Clock Circuits....................57 A.13. System Power....................58 A.13.1. Power Guidelines..................58 A.13.2. Power Distribution System...............59 A.13.3. Power Sequence..................61 A.13.4. Power Measurement................62 A.14.

  • Page 4: Overview

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
  • Page 5 1. Overview 683288 | 2024.04.05 Figure 1. Agilex 7 FPGA I-Series Development Kit Board Diagram This diagram applies to DK-DEV-AGI027RES and DK-DEV-AGI027R1BES. Intel® MAX® 10 Comp -CH0 Comp -CH1 FPGA Conn DDR4 x72 with ECC DDR4 x72 with ECC Intel FPGA...

  • Page 6: Feature Summary

    — Configuration via Protocol (CvP) configuration support — Storage for two configuration images in flash (factory and user) — JTAG header for device programming — Built-in Intel FPGA Download Cable II for device programming • Programmable clock sources — 156.25 MHz differential LVDS for F-tile (QSFPDD) —...

  • Page 7: Box Contents

    1.2. Box Contents Agilex 7 FPGA I-Series development board, DDR4 DIMM module, USB2.0 Micro-USB cable, 240W power adapter, and NA/EU/JP/UK cords. Note: Intel provides only one DIMM module Micron 16GB RDIMM (MTA18ASF2G72PZ-3G2J3) with each development kit. ™ Agilex 7 FPGA I-Series Development Kit User Guide...

  • Page 8: Operating Conditions

    1. Overview 683288 | 2024.04.05 1.3. Operating Conditions Table 2. Recommended Operating Conditions Operating Condition Range Recommended ambient operating temperature range 0°C to 35°C Maximum ICC load current 198 A Maximum ICC load transient percentage Maximum FPGA power supported by the supplied 180 W heatsink/fan Handling Precautions...

  • Page 9: Getting Started

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 10: Installing The Intel Fpga Download Cable Ii Driver

    On the Cable and Adapter Drivers Information web page of the Intel website, locate the table entry for Intel FPGA Download Cable II and click the link to access the instructions. ™ Agilex 7 FPGA I-Series Development Kit User Guide...

  • Page 11: Development Board Setup

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 12: Default Switch Settings

    3. Development Board Setup 683288 | 2024.04.05 3.2. Default Switch Settings This section describes the functionality and default settings for the switches on the board. 3.2.1. Default Settings The Agilex 7 FPGA I-Series Development Kit ships with its board switches preconfigured to support the design examples in the kit.
  • Page 13 4: FPGA PMBUS SDM_I2C Bus disable SDM_I2C Bus Enable enable SW5[1:4] OFF/OFF/OFF/X On-board Intel FPGA Download Cable II is the JTAG host when the external JTAG header (J10) is unoccupied. Type 1: JTAG input source PCIe EP Edge On-Board Intel connector...
  • Page 14 4: FPGA PMBUS SDM_I2C Bus disable SDM_I2C Bus Enable enable SW8[1:4] OFF/OFF/OFF/X On-board Intel FPGA Download Cable II is the JTAG host when the external JTAG header (J10) is unoccupied. Type 1: JTAG input source PCIe EP Edge On-Board Intel connector...
  • Page 15 3. Development Board Setup 683288 | 2024.04.05 Figure 4. SW1[1:4] Switch Setting Figure 5. SW2[1:4] Switch Setting ™ Agilex 7 FPGA I-Series Development Kit User Guide Send Feedback...
  • Page 16 3. Development Board Setup 683288 | 2024.04.05 Figure 6. SW3[1:4] Switch Setting Figure 7. SW4[1:4] Switch Setting Figure 8. SW5[1:4] Switch Setting ™ Agilex 7 FPGA I-Series Development Kit User Guide Send Feedback...
  • Page 17 QSFPDD_0 connector — QSFPDD_1 connector — USB connector For programming the FPGA using on- board Intel FPGA Download Cable II External JTAG header For use with the external download cable DIMM A connector DDR4 Dual DIMM A DIMM B connector...

  • Page 18: Perform Board Restore Through Quartus Prime Programmer

    3. Development Board Setup 683288 | 2024.04.05 Board Reference Type Description POWER GOOD LED Blue LED: • ON: All powers are good. • OFF: Power failure CONFIG DONE LED Green LED: • ON: FPGA configuration successful • OFF: FPGA configuration failed Over Temp LED Red LED: •...
  • Page 19 3. Development Board Setup 683288 | 2024.04.05 5. Click on the Input Files > Add Bitstream tab to specify a that contains .sof the configuration bitstream. 6. Click on the Configuration Device > Add Device to specify the flash device. In the Device list of the pop-up window, select CFI_2Gb for the configuration flash device.

  • Page 20: How To Program The Generated Pof Image

    3. Development Board Setup 683288 | 2024.04.05 9. Click Generate to generate the file. .pof 3.4. How to Program the Generated POF Image To program the generated POF image, follow these steps: 1. Plug in the USB cable to the USB port J8 (when using J10, DIPSWITCH SW5.3 (DK-DEV-AGI027RES and DK-DEV-AGI027R1BES) and SW8.3 (DK-DEV-AGI027RB and DK-DEV-AGI027-RA) should be off).
  • Page 21 3. Development Board Setup 683288 | 2024.04.05 6. In the Programmer page, click Auto Detect to scan the JTAG devices. 7. Right click the VTAP10 device, Edit > Change Device, change it to MAX 10 > 10M50DAF256. ™ Agilex 7 FPGA I-Series Development Kit User Guide Send Feedback...
  • Page 22 3. Development Board Setup 683288 | 2024.04.05 8. Right click the 10M50DAF256 device, Edit > Attach Flash Device, select Quad SPI Flash Memory QSPI_2Gb. 9. In the Programmer page, click QSPI_2Gb > Change File to select the .pof file. 10. Start the Programmer. ™...

  • Page 23: The Required Smartvid Qsf Assignments To Compile A Design

    3. Development Board Setup 683288 | 2024.04.05 3.5. The Required SmartVID QSF Assignments to Compile a Design If you are creating your own design and want to generate a programming SRAM object file (.sof), you must add the correct SmartVID setting into the Quartus Prime project for the Agilex 7 FPGA development kit to configure successfully.
  • Page 24 3. Development Board Setup 683288 | 2024.04.05 Figure 11. Power Management & VID Settings This applies to DK-DEV-AGI027RES and DK-DEV-AGI027R1BES. set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 set_global_assignment -name USE_CONF_DONE SDM_IO16 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401 set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 47 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00...
  • Page 25 3. Development Board Setup 683288 | 2024.04.05 Figure 12. Power Management & VID Settings This diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 set_global_assignment -name USE_CONF_DONE SDM_IO16 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 47 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00...

  • Page 26: Board Test System

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 27: Set Up Bts Gui Running Environment

    4. Board Test System 683288 | 2024.04.05 Figure 14. BTS GUI (Power Solution 1) This diagram applies to DK-DEV-AGI027RES and DK-DEV-AGI027R1BES. 4.1. Set Up BTS GUI Running Environment To run the BTS GUI, including the Power Monitor and Clock Controller GUIs, you need to download and install Java runtime including OpenJDK and OpenJFX on your system and set up the environment.

  • Page 28: Download Openjfx

    4. For Linux systems, download the JavaFX Linux x64 SDK. 4.1.3. Install OpenJDK and OpenJFX You have two downloaded zip files, follow these steps to install them. 1. On Windows systems, Intel recommend that you to unzip the files and put them in the following directories: C:\Program Files\Java\jre...

  • Page 29: Test The Functionality Of The Development Kit

    4. Board Test System 683288 | 2024.04.05 Figure 16. Windows Console 2. On Linux systems, you need to run the shell script with root privilege. Figure 17. Linux Console Note: The .bat or shell script checks the Java environment settings, copies necessary files, and gives some prompts if the environment is not set up correctly.
  • Page 30 4. Board Test System 683288 | 2024.04.05 Figure 18. The Configure Menu (Power Solution 2) This diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. Figure 19. The Configure Menu (Power Solution 1) This diagram applies to DK-DEV-AGI027RES and DK-DEV-AGI027R1BES. ™ Agilex 7 FPGA I-Series Development Kit User Guide Send Feedback...

  • Page 31: The Sys Info Tab

    4. Board Test System 683288 | 2024.04.05 To configure the FPGA with a test system design, follow these steps: 1. On the Configure menu, click the Configure command that corresponds to the functionality you wish to test. 2. In the dialog box that appears, click Configure to download the corresponding design's SRAM Object File (.sof) to the FPGA.

  • Page 32: Board Information

    4. Board Test System 683288 | 2024.04.05 Board Information The board information control displays static information about your board. • Board Name: Indicates the official name of the board given by the BTS. • Board Revision: Indicates the revision of the board. •...

  • Page 33: Qsys Memory Map

    4. Board Test System 683288 | 2024.04.05 SPI Access Over MAX10 SPI Access Over MAX10 allows you to read and write the data at the address you specify. Qsys Memory Map The Qsys Memory Map control shows the memory map of bts_config.sof design running on your board.
  • Page 34 4. Board Test System 683288 | 2024.04.05 Status The Status control displays the following status information during the loopback test: • PLL Lock: Shows the PLL locked or unlocked state. • Pattern Sync: Shows the pattern synced or not state. The pattern is considered synced when the start of the data sequence is detected.

  • Page 35: Error Control

    4. Board Test System 683288 | 2024.04.05 Data Type The Data Type control specifies the type of data pattern contained in the transactions. Select the following available data types for analysis: • PRBS7: Pseudo-random 7-bit sequences. • PRBS15: Pseudo-random 15-bit sequences. •...

  • Page 36: The Ram Tab

    4. Board Test System 683288 | 2024.04.05 4.2.5.2. The QSFPDD PAM4 Tab Figure 25. The QSFPDD PAM4 Tab Similar control functions with the QSFPDD NRZ tab. 4.2.6. The RAM Tab This tab allows you to read and write DDR4-COMP0, DDR4-COMP1, DDR4-RDIMM0, and DDR4-RDIMM1 memory on your board.

  • Page 37: Performance Indicators

    4. Board Test System 683288 | 2024.04.05 Figure 26. The COMP-O Tab This diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. The following sections describe controls on this tab. Start Initiates DDR4 memory transaction performance analysis. Stop Terminates transaction performance analysis. Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start: •...

  • Page 38: Test Control

    4. Board Test System 683288 | 2024.04.05 Test Control • Test Size: You can choose the size of the memory to test. The available options are 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MB, 1 GB, 4 GB, and 8 GB (default).
  • Page 39 4. Board Test System 683288 | 2024.04.05 Figure 28. The RDIMM-0 Tab This diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. Similar control functions to the DDR4- COMP0 tab, the total size is 16 GB. ™ Agilex 7 FPGA I-Series Development Kit User Guide Send Feedback...

  • Page 40: Control On-Board Clock Through Clock Controller Gui

    4. Board Test System 683288 | 2024.04.05 Figure 29. The RDIMM-1 Tab This diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. Same as RDIMM0. 4.3. Control On-board Clock through Clock Controller GUI The Clock Controller GUI can change the on-board Si5391 programmable PLLs to any customized frequency between 100 Hz and 712.5 MHz.

  • Page 41: Monitor On-Board Power Through Power Monitor Gui

    Sets the programmable oscillator frequency for the selected clock to the value in the output controls for the Si5391. Frequency changes might take several OUTx milliseconds to take effect. You might see glitches on the clock during this time. Intel recommends resetting the FPGA logic after changing frequencies. Import You can generate the register list from the Clockbuilder Pro tool and import it into the Si5391 to update the settings of the RAM.

  • Page 42: Data Record

    4. Board Test System 683288 | 2024.04.05 Note: You cannot run the stand-alone Power Monitor GUI when the BTS or the Clock Controller GUI is running at the same time. Figure 31. Power Monitor GUI The following sections describe the details of the Power Monitor GUI. Display Configure •...

  • Page 43: Identify Test Pass Or Fail-Based On Bts Gui Test Status

    4. Board Test System 683288 | 2024.04.05 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status DDR4 DIMMs Plug the DDR4 DIMM module which is shipped with this development kit in J1/J2. QSFPDD0/QSFPDD1 Plug QSFPDD0/QSFPDD1 loopback module in J3/J4 before you configure the QSFPDD NRZ/PAM4 example build through BTS GUI.

  • Page 44: Document Revision History For The Agilex 7 Fpga I-Series Development Kit User Guide

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
  • Page 45 Updated development kit name to Intel Agilex 7 FPGA I-Series Development Kit. ® • Retitled the document from Intel Agilex I-Series FPGA Development Kit User Guide to Intel Agilex 7 FPGA I-Series Development Kit User Guide. 2023.02.27 Updated the supported DDR4 speed for memory interfaces in the Feature Summary section.
  • Page 46 Updated the PCIe and CXL Interfaces section. • Updated Figure: Intel Agilex I-Series FPGA Development Board Image—Front. • Updated the header of Table: Intel Agilex I-Series FPGA Development Kit Ordering Information. • Updated Table: Factory Default Switch Settings. • Removed the Factory Reset section.

  • Page 47: Development Kits Components

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 48: Agilex 7 Fpga I-Series

    A. Development Kits Components 683288 | 2024.04.05 Figure 34. Agilex 7 FPGA I-Series Development Board Image—Back For DK-DEV-AGI027RES and DK-DEV-AGI027R1BES AGIPCIE8000001 Figure 35. Agilex 7 FPGA I-Series Development Board Image—Back For DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. A.2. Agilex 7 FPGA I-Series Agilex 7 FPGA I-Series 56 mm x 45 mm package: •...

  • Page 49: Pcie And Cxl Interfaces

    CXL IP license is required for proper use with the Quartus Prime Design Software. Contact your local Intel sales representative for pricing details. To activate a free-of-charge 30- or 60-days trial IP license, please contact your local Intel sales representative.

  • Page 50: Mcio Cable Assembly Information

    A.5. MCIO Cable Assembly Information The cable is not provided with the development kit. For more information, contact Intel Premier Support and quote ID #14016163317. A.6. Network Interfaces The development kit supports two QSFPDD connectors each, connecting to the Agilex 7's F-tile (12A) transceivers.

  • Page 51: Port Controller

    A. Development Kits Components 683288 | 2024.04.05 aggregator that makes up the Dual 100Gpbs Ethernet interfaces. The FPC202 aggregates all low speed and I2C signals across two ports and presents it as a single management interface to the host. The F-tile (12A) of the FPGA provides 16 general-purpose (FGT) transceiver channels, each 8-channel group is routed to one QSFPDD.

  • Page 52: Fpga Configuration

    Object File (.sof). FPGA Configuration Setup Ensure the following: • The Quartus Prime Programmer and the Intel FPGA Download Cable II driver are installed on the host computer. • The micro-USB cable is connected to the FPGA development board. •...

  • Page 53: Supported Configuration Modes

    DIP switch SW8. The embedded Intel FPGA Download Cable II (or external download cable) or PCIe JTAG can be selected as the source for programming the devices on the chain. The embedded Intel FPGA Download Cable II is the default setting for this configuration mode.
  • Page 54 Intel MAX 10 Download Cable The on-board Intel FPGA Download Cable II is implemented in an MAX 10 device. A micro-USB connector connects to a CY7C68013A USB2 PHY provides the data to MAX 10. This allows configuration of the FPGA using a USB cable directly connected to a PC running the Quartus Prime software without requiring the external download cable dongle.

  • Page 55: Memory Interfaces

    A. Development Kits Components 683288 | 2024.04.05 A.10. Memory Interfaces This memory information applies to DK-DEV-AGI027RES and DK-DEV-AGI027R1BES. Three independent memory interfaces are supported: Two independent on-board DDR4 and one dual DIMM sockets for DDR4. • The on-board DDR4 uses five 16 Gb DDR4 single rank devices connecting to Bank 2B, 2E for memory component channel 0 and bank 2C, 2F for memory component channel 1.
  • Page 56 A. Development Kits Components 683288 | 2024.04.05 Table 9. I2C Device Address Type Address Device FPGA/MAX 10 I2C Address I2C1 0x74 Si5391 0x6A Si52204 0x42 LTM4678/LTM4680 0x45 LTM4686 0x46 LTM4686 I2C2 0x1E FPC202 0x57/0x5F M24128 0x38 MAX31730 0x3A MAX31730 0xA0 QSFPDD_0 0xA0 QSFPDD_1...

  • Page 57: Clock Circuits

    A. Development Kits Components 683288 | 2024.04.05 A.12. Clock Circuits All clocks are supplied by three on-board low-jitter programmable clock generator circuits. The following is the clock connection diagram to the Agilex 7 FPGA. For detailed clock connections, refer to the schematic. •...

  • Page 58: System Power

    A. Development Kits Components 683288 | 2024.04.05 A.13. System Power This section describes the Agilex 7 FPGA I-Series development board's power supply. A laptop style DC power supply is provided with the development kit. Use only the supplied power supply. The power supply has an auto sensing input voltage of 100 ~ 240 V AC power and output 12 V DC power at 20 A to the development board.

  • Page 59: Power Distribution System

    A. Development Kits Components 683288 | 2024.04.05 Figure 44. Powering Board Using Included Power Supply Included Power A.13.2. Power Distribution System The following figure below shows the power distribution system on the Agilex 7 FPGA I-Series development board. ™ Agilex 7 FPGA I-Series Development Kit User Guide Send Feedback...
  • Page 60 A. Development Kits Components 683288 | 2024.04.05 Figure 45. Power Tree Diagram This diagram applies to DK-DEV-AGI027RES and DK-DEV-AGI027R1BES. DDR4 4-phase FPGA_VCC_EN ED8401 0.8V VCC (174A) / VCCP (21.34A) +ET6160 x4 U56,U57,U58,U60 0.8V 17.26A VCC_HSSI_GXF_12A (17.26A) VCCL_SDM EM2120L (0.39A) 12V_G1 ATX 2x4 FB29 0.02A...

  • Page 61: Power Sequence

    A. Development Kits Components 683288 | 2024.04.05 Figure 46. Power Tree Diagram This diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. 12V_GROUP1 12V ATX 2x4 12V_G1 MOSFET MOSFET 12V (DDR4) PWR Conn LTC3888IUHG + LTC7051AV x4 FPGA_VCC U119 + U120, POWER_ON U121, U125, G1_EN LTC4357 Ideal LTC4365 Slew...

  • Page 62: Power Measurement

    A. Development Kits Components 683288 | 2024.04.05 Figure 47. Power Sequence Power Sequence 12V_PCIe Slot (Grp2) Power In 12V_AUX (Grp1) Power_On 1p2V_PRE 1p8V_PRE Power Ok 3p3V_STBY Group 1 Power On 2p5V_PRE FPGA_VCC/CCP VCCPLLDIG_SDM VCCH/VCCH_SDM VCCL_HPS VCCPLLDIG_HPS VCC_HSSI_GXF VCCERT_FGT_GXF Group1_PG VCCRT_GXR VCC_HSSI_GXR Group 2 Power On VCCED_GXR...

  • Page 63: Temperature Monitoring

    A. Development Kits Components 683288 | 2024.04.05 For DK-DEV-AGI027RES and DK-DEV-AGI027R1BES, the following power rails are monitored: 1. VCC, VCCP (Power sensing by I2C on ED8401 2. 0.8V (Power sensing by I2C on EM2120L (U72) 3. 1.2V (Power sensing by I2C on EM2120L (U65) 4.

  • Page 64: Mechanical Requirements

    A. Development Kits Components 683288 | 2024.04.05 A.15. Mechanical Requirements The board is a PCIe standard-height (4.376 in tall), 10” long, dual-slot (1.37 in high above the top surface of the PCB) form factor as defined by the PCIe CEM specification Revision 3.0.

  • Page 65: Board Operating Conditions

    A. Development Kits Components 683288 | 2024.04.05 The heatsink is securely mounted to the board using screws for easy assembly and removal. A thermal material is also used between the FPGA and heatsink to ensure good thermal contact. Figure 51. Air-Cooled Heatsink Assembly A.17.

  • Page 66: Additional Information

    Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 67: Safety Warnings

    B. Additional Information 683288 | 2024.04.05 B.1.1. Safety Warnings Power Supply Hazardous Voltage AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply. Power Connect and Disconnect The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system.

  • Page 68: Power Cord Requirements

    B. Additional Information 683288 | 2024.04.05 Power Cord Requirements The plug on the power cord must be a grounding-type male plug designed for use in your region. It must have certification marks showing certification by an agency in your region. The connector that plugs into the appliance inlet of the power supply must be an IEC 320, sheet C13, female connector.

  • Page 69: Cooling Requirements

    B. Additional Information 683288 | 2024.04.05 Cooling Requirements Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan. Electro-Magnetic Interference (EMI) This equipment has not been tested for compliance with emission limits of FCC and similar international regulations.

  • Page 70: Electrostatic Discharge (Esd) Warning

    Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.

  • Page 71: Compliance Information

    B. Additional Information 683288 | 2024.04.05 Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of product in unsorted municipal waste. B.2. Compliance Information...

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