Download
Share
Print this page
Intel altera Cyclone V SoC User Manual
  1. Manuals
  2. Brands
  3. Intel Manuals
  4. Microcontrollers
  5. altera Cyclone V SoC
  6. User manual

Intel altera Cyclone V SoC User Manual

Hide thumbs

Advertisement

Quick Links

Download this manual
Explore more resources
®
Altera
Design Hub
®
Cyclone
User Guide
Online Version
Send Feedback
V SoC Development Kit
830285
2024.10.07

Advertisement

loading
Need help?

Need help?

Do you have a question about the altera Cyclone V SoC and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Intel altera Cyclone V SoC

Summary of Contents for Intel altera Cyclone V SoC

  • Page 1 Explore more resources ® Altera Design Hub ® Cyclone V SoC Development Kit User Guide 830285 Online Version Send Feedback 2024.10.07...

  • Page 2: Table Of Contents

    2.3.1. Installing the Quartus Prime Standard Edition Software.........11 2.3.2. Installing the Intel SoC EDS..............11 2.3.3. Installing the Development Kit..............12 2.3.4. Installing the Intel FPGA Download Cable II Driver........12 3. Development Kit Setup....................14 3.1. Setting Up the Development Kit................14 3.2.
  • Page 3 Contents A.2.3. SD Card Memory..................50 A.3. Power........................ 51 B. Additional Information....................53 B.1. Safety and Regulatory Information.................53 B.1.1. Safety Warnings..................54 B.1.2. Safety Cautions..................55 B.2. Compliance Information..................58 ® Cyclone V SoC Development Kit User Guide Send Feedback...

  • Page 4: Overview

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 5 1. Overview 830285 | 2024.10.07 Figure 2. Cyclone V SoC Development Kit (Power Solution 1)—Top View Refer to the Appendix A—Development Kit Components section for more details about the components on the Cyclone V SoC Development Kit. Related Information Development Kit Components on page 45 ®...

  • Page 6: Block Diagram

    1. Overview 830285 | 2024.10.07 1.1. Block Diagram Figure 3. Cyclone V SoC Development Kit Block Diagram LTC Power MAX® V I2C Header Mini-USB On-Board Intel® FPGA DIPSW USB2 Download Cable II UART Real-Time (3:0) (3:0) (3:0) and USB interface...

  • Page 7: Feature Summary

    • Cyclone V SX SoC—5CSXFC6D6F31C6N (SoC) ® • V CPLD—5M2210ZF256C4N (system controller) ® • MAX II CPLD—EPM570GF100 (embedded Intel FPGA Download Cable II) FPGA I/O Interfaces • 2 10/100 Megabit Ethernet PHYs (EtherCAT) • PCIe* 1.0 x4 female connector •...

  • Page 8: Cables And Adapters

    ® A one-year license for the Quartus Prime Pro Edition design software is included with the purchase of the kit. Refer to the Intel FPGA Software Installation and Licensing for more information. Related Information Intel FPGA Software Installation and Licensing ®...

  • Page 9: Box Contents

    1. Overview 830285 | 2024.10.07 1.3. Box Contents • Cyclone V development board—A development platform that allows you to develop and prototype hardware designs running on the Cyclone V SoC. • MicroSD flash memory card • Debug header breakout board high-speed mezzanine card (HSMC) •...

  • Page 10: Getting Started

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 11: Installing The Quartus Prime Standard Edition Software

    SoC embedded systems. As a part of the Intel SoC EDS, the Arm* Development Studio 5 (DS-5) Intel SoC FPGA Edition Toolkit provides a comprehensive set of embedded development tools for Altera's SoC FPGAs.

  • Page 12: Installing The Development Kit

    The Cyclone V SoC Development Kit includes onboard Intel FPGA Download Cable circuits for FPGA and system MAX V programming. However, for the host computer and board to communicate, you must install the Intel FPGA Download Cable driver on the host computer.
  • Page 13 2. Getting Started 830285 | 2024.10.07 On the Intel website, navigate to the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions. Related Information Cable and Adapter Drivers Information ®...

  • Page 14: Development Kit Setup

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 15: Factory Default Switch And Jumper Settings

    3. Development Kit Setup 830285 | 2024.10.07 3.2. Factory Default Switch and Jumper Settings Cyclone V SoC Development Kit (Power Solution 2) and Cyclone V SoC Development Kit (Power Solution 1) ship with their board switches preconfigured to support the design examples in the development kits.
  • Page 16 OFF (1)—Parallel flash loader (PFL) disabled. Security Switch 4 has the following options: • ON (0)—Onboard Intel FPGA Download Cable II sends FACTORY command at power up. • OFF (1)—Onboard Intel FPGA Download Cable II does not send FACTORY command at power up.
  • Page 17 3. Development Kit Setup 830285 | 2024.10.07 In the following table, up and down indicates the position of the switch with the board orientation as shown in the Switch Locations and Default Settings for Power Solution 2 figure. Table 5. SW4 JTAG DIP Switch Settings Switch Board Label...
  • Page 18 Intel FPGA Download Cable II from driving the HPS JTAG input port in this mode. JTAG SEL • SHORT—The Intel FPGA Download Cable II is the SHORT source of the JTAG chain. • OPEN—The Mictor is the source of the JTAG chain.

  • Page 19: Restoring The Default Settings For Power Solution 1 Board

    OFF (1)—Parallel flash loader (PFL) disabled. Security Switch 4 has the following options: • ON (0)—Onboard Intel FPGA Download Cable II sends FACTORY command at power up. • OFF (1)—Onboard Intel FPGA Download Cable II does not send FACTORY command at power up.
  • Page 20 3. Development Kit Setup 830285 | 2024.10.07 In the following table, up and down indicates the position of the switch with the board orientation as shown in the Switch Locations and Default Settings for Power Solution 1 figure. Important: The default MSEL pin settings are set to all zeroes (ON) to select the fast passive parallel x16 mode.
  • Page 21 Intel FPGA Download Cable II from driving the HPS JTAG input port in this mode. JTAG SEL • SHORT—The Intel FPGA Download Cable II is the SHORT source of the JTAG chain. • OPEN—The Mictor is the source of the JTAG chain.

  • Page 22: Restoring The Max V Cpld To The Factory Setting

    1. On the Tools menu in the Quartus Prime software, click Programmer. 2. In the Programmer window, click Auto-Detect. Note: If you do not see Intel FPGA Download Cable or the board's embedded Intel FPGA Download Cable II listed next to Hardware Setup, refer to the Quartus Prime Software and Driver Installation section.
  • Page 23 Power Monitor, Clock Control, or other logic functions. Use the flash writer only for flash programming. To ensure that you have the most up-to-date factory restore files and information about this product, refer to the Cyclone V SoC Development Kit webpage of the Intel website. Related Information •...

  • Page 24: Board Update Portal

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 25 Portal web page to access the kit's home page for documentation updates and additional new designs. You can also navigate directly to the Cyclone V SoC Development Kit webpage of the Intel website to determine if you have the latest kit software. ® Cyclone...

  • Page 26: Board Test System

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 27: Preparing The Board For The Board Test System

    5.1. Preparing the Board for the Board Test System With the power to the board off, follow these steps: 1. Plug the included USB cable from J37 (Intel FPGA Download Cable II interface) to the host computer's USB port. 2. Ensure that the development board switches and jumpers are set to the default positions as shown in the Factory Default Switch and Jumper Settings section.

  • Page 28: Using The Board Test System

    MAX V ver: Indicates the version of MAX V code currently running on the board. The MAX V code resides in the cycloneVSX_5csxfc6df31_soc\examples directory. Newer revisions of this code might be available on the Cyclone V SoC Development Kit webpage of the Intel website. ® Cyclone V SoC Development Kit User Guide...
  • Page 29 Cyclone V device is always the first device in the chain. The JTAG chain is normally mastered by the onboard Intel FPGA Download Cable II. Note: If you plug in an external onboard Intel FPGA Download Cable cable to the JTAG header (J23), the onboard Intel FPGA Download Cable II is disabled. Note: JTAG DIP switch bank (SW4) selects which interfaces are in the chain.

  • Page 30: The Gpio Tab

    5. Board Test System 830285 | 2024.10.07 5.3.3. The GPIO Tab The GPIO tab allows you to interact with all the general-purpose user I/O components on your board. You can write to the character LCD, read DIP switch settings, turn LEDs on or off, and detect push button presses.

  • Page 31: The I2C Tab

    5. Board Test System 830285 | 2024.10.07 5.3.4. The I2C Tab The I2C tab allows you to read and write 1 kilobit (Kb) to an I2C EEPROM located at U28 on the development board Figure 11. The I2C Tab The following sections describe the controls on the I2C tab. EEPROM The serial I C EEPROM is 32 Kilobits.

  • Page 32: The Ddr3 Tab

    5. Board Test System 830285 | 2024.10.07 5.3.5. The DDR3 Tab The DDR3 tab allows you to read and write the DDR3 memory on your board. Figure 12. The DDR3 Tab The following sections describe the controls on the DDR3 tab. Start The Start control initiates DDR3 memory transaction performance analysis.
  • Page 33 5. Board Test System 830285 | 2024.10.07 Error Control The Error control control displays data errors detected during analysis and allows you to insert errors: • Detected errors: Displays the number of data errors detected in the hardware. • Inserted errors: Displays the number of errors inserted into the transaction stream.

  • Page 34: The Sdi Video Tab

    5. Board Test System 830285 | 2024.10.07 5.3.6. The SDI Video Tab The SDI Video tab allows you to test the SDI video interface on your board. Figure 13. The SDI Video Tab The following sections describe the controls on the SDI Video tab. ®...

  • Page 35: Pattern Generator

    5. Board Test System 830285 | 2024.10.07 Pattern Generator This control specifies the test pattern to output to the monitor. The following choices are available: • Color bar: Specifies a video color bar pattern with eight vertical color bars as shown in table below.
  • Page 36 5. Board Test System 830285 | 2024.10.07 • Inserted errors: Displays the number of errors inserted by clicking Insert Error button. • Detected errors: Displays the number of bit errors detected by the error checking circuitry. • BER: Displays the bit error rate of the interface. •...

  • Page 37: The Hsmc Tab

    5. Board Test System 830285 | 2024.10.07 5.3.7. The HSMC Tab The HSMC tab allows you to perform loopback tests on the XCVR, LVDS, and CMOS ports. Note: This tab requires that a file with QTS=ON specified at the 1st line reside in bts.ini the same directory as .
  • Page 38 5. Board Test System 830285 | 2024.10.07 • Detected errors: Displays the number of bit errors detected by the error checking circuitry. • BER: Displays the bit error rate of the interface. • PLL lock: Displays Yes if the SDI PLL is locked. •...

  • Page 39: The Power Monitor

    5. Board Test System 830285 | 2024.10.07 5.4. The Power Monitor The Power Monitor measures and reports current power information. To start the application, click Power Monitor in the Board Test System application. Attention: You can also run the Power Monitor as a stand-alone application. PowerMonitor.bat resides in the cycloneVSX_5csxfc6df31_soc\examples\board_test_system...
  • Page 40 5. Board Test System 830285 | 2024.10.07 • Temp on 2978: The temperature controls display only the temperature from the power supply manager, not the FPGA. • Total Power: These controls display the sum of all four rails for each group, U34 and for U26.

  • Page 41: The Clock Control

    5. Board Test System 830285 | 2024.10.07 5.5. The Clock Control The Clock Control application sets the Si570 or Si571 programmable oscillators to any frequency between 10 MHz and 810 MHz and Si5338. The frequencies support eight digits of precision to the right of the decimal point. The Clock Control application runs as a stand-alone application.
  • Page 42 5. Board Test System 830285 | 2024.10.07 Target Frequency The Target frequency control allows you to specify the frequency of the clock. Legal values are between 10 and 810 MHz with eight digits of precision to the right of the decimal point.

  • Page 43: Configuring The Fpga Using The Quartus Prime Programmer

    JTAG chain, do the following: • Click Hardware Setup in the Quartus Prime Programmer window. • Reselect Intel FPGA Download Cable II in order to properly detect the JTAG chain. 5.6.2. Configuring the FPGA Perform these steps: 1. Start the Quartus Prime Programmer.

  • Page 44: Document Revision History For The Cyclone V Soc Development Kit User Guide

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 45: Development Kit Components

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 46: Programming Flash Memory

    (S10, S11, S12) (J35) for Onboard Connector 2 (J36) (J32) (J25) Connector 1 Intel® FPGA (J33) (J34) Download Cable (J37) A.2. Programming Flash Memory This appendix describes programming information for the following memory devices: • Common flash interface (CFI) flash memory •...

  • Page 47: Cfi Flash Memory

    The Altera CPLD JTAG block interfaces directly with the logic array in a special JTAG mode. This mode brings the JTAG chain through the logic array instead of the Altera CPLD boundary-scan cells (BSC). The Parallel Flash Loader Intel FPGA IP provides JTAG interface logic to do the following: •...
  • Page 48 1. On the Tools menu in the Quartus Prime software, click Programmer. 2. In the Programmer window, click Auto-Detect. Note: If you do not see Intel FPGA Download Cable or the board's embedded Intel FPGA Download Cable II listed next to Hardware Setup, refer to the Cable and Adapter Drivers Information webpage in the Intel website.

  • Page 49: Quad Spi Flash Memory

    A. Development Kit Components 830285 | 2024.10.07 To convert the files, follow these steps: 1. On the File menu, click Convert Programming Files. 2. For Programming file type, specify Programmer Object File (.pof) and name the file. 3. For Configuration device, select CFI_512Mb for this kit's CFI device. 4.

  • Page 50: Sd Card Memory

    Attention: Be careful when using this programming command as it overwrites whatever that is found on the device pointed to in the command. For more information, refer to the Intel SoC FPGA Embedded Development Suite (SoC EDS) User Guide and RocketBoards.org. Related Information Intel SoC FPGA Embedded Development Suite (SoC EDS) User Guide ®...

  • Page 51: Power

    A. Development Kit Components 830285 | 2024.10.07 A.3. Power Figure 21. Cyclone V SoC Development Kit (Power Solution 2) Power Tree MPM 3650CGQW 1.1 V 1.1V_HPS 0.207 A Switching C5SX HPS VCC Regulator (3A) 1.923 A MPM 3650CGQW 1.5 V 0.469 A 1.5V_HPS Switching...
  • Page 52 A. Development Kit Components 830285 | 2024.10.07 Figure 22. Cyclone V SoC Development Kit (Power Solution 1) Power Tree EN2342QI 1.1 V VCCINT_HPS 0.2 A Switching C5SX HPS VCC Regulator (3A) 1.5 A EN2342QI 1.5 V 0.4 A Switching VCCIO, VDD - DDR3 Regulator (3A) 2.6 A VCCPD, VCCIO,...

  • Page 53: Additional Information

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 54: Safety Warnings

    B. Additional Information 830285 | 2024.10.07 B.1.1. Safety Warnings Power Supply Hazardous Voltage AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply. Power Connect and Disconnect The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system.

  • Page 55: Safety Cautions

    B. Additional Information 830285 | 2024.10.07 Power Cord Requirements The plug on the power cord must be a grounding-type male plug designed for use in your region. It must have certification marks showing certification by an agency in your region. The connector that plugs into the appliance inlet of the power supply must be an IEC 320, sheet C13, female connector.
  • Page 56 B. Additional Information 830285 | 2024.10.07 Cooling Requirements Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan. Electro-Magnetic Interference (EMI) This equipment has not been tested for compliance with emission limits of FCC and similar international regulations.
  • Page 57 Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.

  • Page 58: Compliance Information

    B. Additional Information 830285 | 2024.10.07 Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of product in unsorted municipal waste. B.2. Compliance Information...

This manual is also suitable for:

5csxfc6d6f31c6n