Rcc Register Map; Table 15. Rcc Register Map And Reset Values - ST STM32F100 Series Reference Manual

RM0041
6.3.12

RCC register map

The following table gives the RCC register map and the reset values.
Offset Register
RCC_CR
0x000
Reset value
RCC_CFGR
0x004
Reset value
RCC_CIR
0x008
Reset value
RCC_APB2RSTR
0x00C
Reset value
RCC_APB1RSTR
0x010
Reset value
RCC_AHBENR
0x014
Reset value
RCC_APB2ENR
0x018
Reset value
RCC_APB1ENR
0x01C
Reset value
RCC_BDCR
0x020
Reset value
RCC_CSR
0x024
Reset value 0
RCC_CFGR2
0x02C
Reset value
Refer to

Table 15. RCC register map and reset values

Reserved
0 0
MCO [2:0]
Reserved
0 0 0
Reserved
0
Reserved
Reserved
0 0 0
Reserved
0 0 0 0
Reserved
0 0 0 1 1 0
Table 1 on page 37 and
Reserved
0 0 0 0 0
ADC
PLLMUL[3:0] PRE
[1:0]
0 0 0 0 0 0 0
0 0 0 0 0
0 0 0
0 0 0 0 0 0 0
Reserved
0 0 0
0 0 0 0 0 0 0
0 0
Reserved
Table 2 on page 38
RM0041 Rev 6
Reset and clock control (RCC)
HSICAL[7:0] HSITRIM[4:0]
0 0 0 0 0 0 0 1 0
PPRE2 PPRE1
HPRE[3:0]
[2:0] [2:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0
0 0
0 0 0 0 0 0 0
0 0 0 0 0
RTC
SEL
Reserved Reserved
[1:0]
0 0
Reserved
for the register boundary addresses.
0 0 0 1 1
SWS SW
[1:0] [1:0]
0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0
1 1 0 0
0 0 0 0 0
0 0 0 0 0 0
0 0 0
0 0
PREDIV1[3:0]
0 0 0 0
101/709
101