ST STM32F100 Series Reference Manual page 545

RM0041
Start sequence in master mode
•
In full-duplex (BIDIMODE=0 and RXONLY=0)
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–
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• In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)
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–
•
In bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1)
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–
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• In bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0)
–
–
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Start sequence in slave mode
• In full-duplex mode (BIDIMODE=0 and RXONLY=0)
–
–
•
In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)
–
–
•
In bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1)
–
–
The sequence begins when data are written into the SPI_DR register (Tx buffer).
The data are then parallel loaded from the Tx buffer into the 8-bit shift register
during the first bit transmission and then shifted out serially to the MOSI pin.
At the same time, the received data on the MISO pin is shifted in serially to the 8-
bit shift register and then parallel loaded into the SPI_DR register (Rx buffer).
The sequence begins as soon as SPE=1
Only the receiver is activated and the received data on the MISO pin are shifted in
serially to the 8-bit shift register and then parallel loaded into the SPI_DR register
(Rx buffer).
The sequence begins when data are written into the SPI_DR register (Tx buffer).
The data are then parallel loaded from the Tx buffer into the 8-bit shift register
during the first bit transmission and then shifted out serially to the MOSI pin.
No data are received.
The sequence begins as soon as SPE=1 and BIDIOE=0.
The received data on the MOSI pin are shifted in serially to the 8-bit shift register
and then parallel loaded into the SPI_DR register (Rx buffer).
The transmitter is not activated and no data are shifted out serially to the MOSI
pin.
The sequence begins when the slave device receives the clock signal and the first
bit of the data on its MOSI pin. The 7 remaining bits are loaded into the shift
register.
At the same time, the data are parallel loaded from the Tx buffer into the 8-bit shift
register during the first bit transmission, and then shifted out serially to the MISO
pin. The software must have written the data to be sent before the SPI master
device initiates the transfer.
The sequence begins when the slave device receives the clock signal and the first
bit of the data on its MOSI pin. The 7 remaining bits are loaded into the shift
register.
The transmitter is not activated and no data are shifted out serially to the MISO
pin.
The sequence begins when the slave device receives the clock signal and the first
bit in the Tx buffer is transmitted on the MISO pin.
The data are then parallel loaded from the Tx buffer into the 8-bit shift register
during the first bit transmission and then shifted out serially to the MISO pin. The
RM0041 Rev 6
Serial peripheral interface (SPI)
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