Auto-Wakeup (Awu) From Low-Power Mode; Power Control Registers; Power Control Register (Pwr_Cr) - ST STM32F100 Series Reference Manual

Power control (PWR)
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except:
•
Reset pad (still available)
•
TAMPER pin if configured for tamper or calibration out
•
WKUP pin, if enabled
Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Cortex
no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 25.15.1: Debug support for low-power
4.3.6

Auto-wakeup (AWU) from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an
external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for
waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three
alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the
Backup domain control register
•
Low-power 32.768 kHz external crystal oscillator (LSE OSC).
This clock source provides a precise time base with very low-power consumption (less
than 1µA added consumption in typical conditions)
•
Low-power internal RC Oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.
To wakeup from Stop mode with an RTC alarm event, it is necessary to:
•
Configure the EXTI Line 17 to be sensitive to rising edge
•
Configure the RTC to generate the RTC alarm
To wakeup from Standby mode, there is no need to configure the EXTI Line 17.
4.4

Power control registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
4.4.1

Power control register (PWR_CR)

Address offset: 0x00
Reset value: 0x0000 0000 (reset by wakeup from Standby mode)
31 30 29
15 14 13
Reserved
60/709
28 27 26 25
12 11 10 9
modes.
(RCC_BDCR):
24 23 22
Reserved
8 7 6
DBP PLS[2:0]
rw rw rw
RM0041 Rev 6
21 20 19 18
5 4 3 2
PVDE CSBF CWUF
rw rw rc_w1 rc_w1
RM0041
®
-M3 core is
17 16
1 0
PDDS LPDS
rw rw