Debug Mode; Table 88. Minimum And Maximum Timeout Values @24 Mhz (F Pclk1 ) - ST STM32F100 Series Reference Manual

Window watchdog (WWDG)
As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3
and T[5:0] is set to 63:
Refer to
Prescaler
1
2
4
8
19.5

Debug mode

When the microcontroller enters debug mode (Cortex
either continues to work normally or stops, depending on DBG_WWDG_STOP
configuration bit in DBG module. For more details, refer to
for timers, watchdog and I
490/709
t WWDG = 1
Table 88 for the minimum and maximum values of the t
Table 88. Minimum and maximum timeout values @24 MHz (f
WDGTB
0
1
2
3
2
C.
3
⁄ × ×
24000 4096 2
Min timeout value
170.67 µs
341.33 µs
682.67 µs
1365.33 µs
RM0041 Rev 6
× ( )
63 + 1 = 87.38ms
.
WWDG
Max timeout value
10.92 ms
21.85 ms
43.69 ms
87.38 ms
®
-M3 core halted), the WWDG counter
Section 25.15.2: Debug support
RM0041
)
PCLK1