ST STM32F100 Series Reference Manual page 432

General-purpose timers (TIM15/16/17)
Bit 15 MOE: Main output enable
Bit 14 AOE: Automatic output enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 13 BKP: Break polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR: Off-state selection for Run mode
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
432/709
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details
enable register (TIM15_CCER) on page
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
in TIMx_BDTR register).
0: Break input BRK is active low
1: Break input BRK is active high
in TIMx_BDTR register).
0: Break inputs (BRK and CSS clock failure event) disabled
1; Break inputs (BRK and CSS clock failure event) enabled
TIMx_BDTR register).
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details
enable register (TIM15_CCER) on page
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
bits in TIMx_BDTR register).
(Section 15.5.8: TIM15 capture/compare
426).
(Section 15.5.8: TIM15 capture/compare
426).
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