Cec States; Figure 279. Cec Control State Machine - ST STM32F100 Series Reference Manual

RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™-
24.7.7

CEC states

Figure 279
The CEC controller assumes one of the six states described below:
Disabled state
The Disabled state is entered either on an APB reset or on resetting the PE bit in the CEC
configuration register. Any ongoing transmission or reception is not interrupted and
completes normally. The controller actually switches to Disabled when the PE bit is read
back as 0. While the controller is in the Disabled state, activity on the CEC line is ignored
and the clock prescaler is stopped for minimum power consumption purposes. The
controller exits the Disabled state when the PE bit is set.
Idle state
The Idle state is entered whenever a message was transmitted or received successfully, or
an error was processed. While in the Idle state, the CEC controller waits for either a transmit
request (TSOM bit is set in the control status register) or a start bit.
RX state
The CEC controller enters the RX state when a start bit is detected and no message is
pending for transmission. Once the header has been received, the destination address is
compared to the value programmed in the own address register. If the two do not match and
the address is not the broadcast address 0xF, the block is not acknowledged and the
controller reverts to the Idle state. Otherwise, in case of a match, the controller remains in
the RX state where the host CPU is requested to retrieve all message bytes from the RX
buffer one by one. An available byte is signaled by the RBTF bit being set in the control
shows the CEC controller state machine.

Figure 279. CEC control state machine

PE = 0
TSOM = 1
TX
TEOM = 1
TX_ERROR
TERR = 0
RM0041 Rev 6
Reset
Disabled
PE = 1
Idle
Start bit & TSOM = 0
Arbitration lost
TERR = 1 RERR = 1
RX_ERROR
RX
REOM = 1 or
no address match
RERR = 0
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