Debug support (DBG)
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
•
Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles must be applied while driving the line low (IDLE state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it fails.
25.8.5
SW-DP registers
Access to these registers are initiated when APnDP=0
A[3:2]
00
Read
00
Write
01
Read/Write
01
Read/Write
10
Read
10
Write
11
Read/Write
25.8.6
SW-AP registers
Access to these registers are initiated when APnDP=1
There are many AP registers (see AHB-AP) addressed as the combination of:
•
The shifted value A[3:2]
•
The current value of the DP SELECT register
682/709
Table 152. SW-DP registers
CTRLSEL bit
R/W
of SELECT
register
-
-
0
1
-
-
-
RM0041 Rev 6
Register
The manufacturer code is not set to ST code.
IDCODE
0x1BA01477 (identifies the SW-DP)
ABORT
Purpose is to:
– request a system or debug power-up
– configure the transfer operation for AP
DP-
accesses
CTRL/STAT
– control the pushed compare and pushed verify
operations.
– read some status flags (overrun, power-up
acknowledges)
Purpose is to configure the physical serial port
WIRE
protocol (like the duration of the turnaround
CONTROL
time)
Enables recovery of the read data from a
READ
corrupted debugger transfer, without repeating
RESEND
the original AP transfer.
The purpose is to select the current access port
SELECT
and the active 4-words register window
This read buffer is useful because AP accesses
are posted (the result of a read AP request is
available on the next AP transaction).
READ
BUFFER
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction
RM0041
Notes
-
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