Hdmi-Cec Registers; Cec Configuration Register (Cec_Cfgr) - ST STM32F100 Series Reference Manual

RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™-
24.9

HDMI-CEC registers

Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
24.9.1

CEC configuration register (CEC_CFGR)

This register is used to configure the HDMI-CEC controller.
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:4 Reserved, must be kept cleared.
Bit 3 BPEM: Bit period error mode
This bit is set/cleared by software.
0: Standard mode
1: Flexible bit-period mode
Bit 2 BTEM: Bit timing error mode
This bit is set/cleared by software.
0: Standard mode
1: Bit timing error-free mode
Bit 1 IE: Interrupt enable
This bit is set/cleared by software. It is used to activate an interrupt associated with the set of
RTBF, RERR, TBTRF or TERR flags.
0: Interrupt disabled
1: Interrupt enabled
Bit 0 PE: Peripheral enable
This bit is set by software, cleared by hardware as soon as the CEC state is Idle.
0: Peripheral disabled
1: Peripheral enabled
Section 1.1 on page 32
28 27 26 25
12 11 10 9
Reserved
for a list of abbreviations used in register descriptions.
24 23 22
Reserved
8 7 6
RM0041 Rev 6
21 20 19 18
5 4 3 2
BPEM BTEM
rw rw
17 16
1 0
IE PE
rw rs
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