Table 112. Fsmc_Bcrx Bit Fields; Figure 216. Multiplexed Write Accesses - ST STM32F100 Series Reference Manual

Flexible static memory controller (FSMC)
The difference with mode D is the drive of the lower address byte(s) on the databus.
Bit No.
31-21
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
516/709

Figure 216. Multiplexed write accesses

A[25:16]
NADV
NEx
NOE
NWE
AD[15:0]
ADDSET
HCLK cycles

Table 112. FSMC_BCRx bit fields

Bit name
Reserved
CBURSTRW
CPSIZE
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
MTYP[0:1]
Memory transaction
Lower address
ADDHLD
HCLK cycles
0x000
0x0 (no effect on asynchronous mode)
0x0 (no effect on asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
0.
0x0
0x0 (no effect on asynchronous mode)
As needed
Don't care
0x0
Meaningful only if bit 15 is 1
0x0
0x1
0x1
As needed
0x2 (NOR flash memory)
RM0041 Rev 6
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
Value to set
RM0041
ai15569